Atari 2600 programming
Harry Dodgson
dodgson at cs.wmich.edu
Sat Jan 28 03:12:42 AEST 1989
Wsync Wait for sync
This address halts microprocessor by clearing RDY latch to zero. RDY is
set true again by the leading edge of horizontal blank.
Data bits not used.
---
Rsync Reset Sync
This address resets the horizontal sync counter to define the begining of
horizontal blank time, and is used in chip testing.
Data bits not used.
---
Vsync
This address controls vertical sync time by writing D1 into the Vsync latch.
D1 - 1: start vertical sync
0: stop vertical sync
---
Vblank
This address controls vertical blank and the latches and dumping transistors
on the input ports by writing into bits D7,D6, and D1 of the Vblank register.
D1 - 1: start vertical blank
0: stop vertical blank
D6 - 1: enable I4 and I5 latches
0: disable latches - also resets latches to logic true
D7 - 1: Dump I0,I1,I2,I3 ports to ground
0: Remove dump path to ground
---
Pf0, Pf1, Pf2
These addresses are used to write into the playfield registers.
horizontal scan line map
(160 clocks, each bit =4 clocks)
Ctrlpf bit 0
bits 4-7 7-0 0-7 | 4-7 7-0 0-7
register Pf0 Pf1 Pf2 Pf0 Pf1 Pf2 0
bits 4-7 7-0 0-7 | 7-0 0-7 7-4
register Pf0 Pf1 Pf2 Pf2 Pf1 Pf0 1
---
Ctrlpf
This address is used to write into the playfield control register.
if bit is 1 then:
D0 - (REF) reflect playfield, see above
D1 - (SCORE) left half of playfield gets color of player 0
right half gets color of player 1
D2 - (PFP) playfield gets priority over players so they move
behind playfield
D5,D4 - Ball Size if 00, 1 clock wide
if 01, 2 clocks wide
if 10, 4 clocks wide
if 11, 8 clocks wide
---
Nusiz0, Nusiz1
These addresses control the number and size of players and missles.
D5,D4 - Missle Size see Ball Size above
D2,D1,D0 - Player number/size
if 000, X one copy
if 001, X X two copies, close
if 010, X X two copies, medium
if 011, X X X three copies, close
if 100, X X Two copies, far
if 101, XX one copy, double width
if 110, X X X 3 copies, medium
if 111, XXXX one copy, quad width
---
Resp0, Resp1, Resm0, Resm1, Resbl
These addresses are used to reset players, missles and the ball. The object
will begin its serial graphics at that time of a horizontal line at which the
reset address occurs.
Data bits not used.
---
Resmp0, Resmp1
These addresses are used to reset the horizontal location of a missle to
the center of its corresponding player. As long as this control bit is
true (1), the misslw will remain locked to the center of its player and the missle graphics will be disabled. When a zero is written into this location,
the missle is enabled, and can be moved independently from the player.
D1 - 0: allow missle to move
1: lock missle to player
---
Hmove
This address causes the horizontal motion register values to be acted upon
during the horizontal blank time in which it occurs. It must occur at the
beginning of horizontal blanking in order to allow time for generation of
extra clock pulses into the horizontal position counters. If motion is
desired, this command must immediately follow a Wsync command in the program.
Data bits not used.
---
Hmclr
This address clears all horizontal motion registers to zero (no motion).
Data bits not used.
---
Hmp0, Hmp1, Hmm0, Hmm1, Hmbl
These addresses write data (horizontal motion values) into the horizontal
motion registers. These registers cause horizontal motion only when commanded
to do so by the horizontal movement command Hmove. The motion values use the
upper 4 bits of the byte. They are signed numbers with a +7 to -8 range. The
positive numbers indicate left movement, the negative indicate right.
Warning: These registers should not be modified during the 24 computer cycles
following an Hmove command. Unpredictable motion values may result.
---
Enam0, Enam1, Enabl
These addresses write into the single bit missle or ball graphics registers.
D1 - 0: disables object
1: enables object
---
Grp0, Grp1
These addresses write data into the player graphics registers
horizontal scan line map
(each bit =1 clock)
bits 7-0 if Refp0 (Refp1) is 0
bits 0-7 if Refp0 (Refp1) is 1 (reflected)
---
Refp0, Refp1
These addresses write data into the the single bit player reflect registers.
see above.
D3 - 0: normal
1: reflected
---
Vdelp0, Vdelp1, Vdelbl
These addresses write data into the single bit vertical delay registers, to
delay players or the ball by one vertical line.
D0 - 0: no delay
1: delayed
---
Cxclr
This address clears all collision latches to zero (no collision)
Data bits not used.
---
Colupb, Colup1, Colupf, Colubk
These addresses write data into the player, playfield, and background
color-luminance registers.
D3, D2, D1 - Luminance values 000 is dark, 111 is bright.
D7,D6,D5,D4 - Colors 0000 Grey
0001 Gold
0010 Orange
0011 Red orange
0100 Pink
0101 Purple
0110 Blue purple
0111 Blue
1000 Blue
1001 Light blue
1010 Turquoise
1011 Green blue
1100 Green
1101 Yellow green
1110 Orange green
1111 Light orange
---
Audf0, Audf1
These addresses write data into the audio frequency divider registers.
D4,D3,D2,D1,D0 - 00000 30KHz divided by 1
00001 " " 2
.....
11111 " " 32
---
Audc0, Audc1
These addresses write data into the audio control registers which control
the noise content and additional division of the audio output.
bits value noise type division
D3, D2, D1, D0 - 0000 set to 1
0001 4 bit poly
0010 /15 into 4 bit poly
0011 5 bit poly into 4 bit poly
0100 divide by 2
0101 divide by 2
0110 divide by 31
0111 5 bit poly into /2
1000 9 bit poly
1001 5 bit poly
1010 divide by 31
1011 set last 4 bits to 1
1100 divide by 6
1101 divide by 6
1110 divide by 93
1111 5 bit poly divided by 6
---
Audv0, Audv1
These addresses write data into the audio volume registers which set the pull
down impedance driving the audio output pads.
D3, D2, D1, D0 - 0000 no output
....
1111 loudest output
---
End
--
Harry Dodgson Jr. Internet: dodgson at cs.wmich.edu
Western Michigan University
Computer Science Department Voice: (616) 387-5803
Kalamazoo, MI 49008
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