ANSII C, optimization, and "hardware registers"

[Brian Thomson]

The 'volatile' keyword will tell an (optimizing) compiler that a
location can change value asynchronously, but sometimes that isn't
enough.
Another common idiosyncrasy of hardware is that it is read-only
or write-only, or can only be accessed using byte or halfword or
fullword accesses.
I believe the Ritchie PDP-11 compiler would compile
		a = b + c;
into
		mov	b,a
		add	c,a
in appropriate circumstances; this clearly will fail if 'a' refers to
a write-only register.
The second situation is exemplified by registers in nexus space
on a Vax (forgive me if you don't know what this means), which
may only be accessed as longwords, and by Unibus registers which
may only be accessed as bytes or halfwords.
A favourite improvement made by /lib/c2 when compiling
		short a;
		...
		if (a&1) ...
is to replace the straightforward
		bitw	$2,_a
		jeql	L1
by
		jlbc	_a,L1
(Jump if Lower Bit Clear, that means) which is fine except that
the first sequence references _a as a halfword while the second
does a longword reference.

( the undocumented "-i" flag to vax /lib/c2 disables
  these optimizations that alter reference size, and doesn't have
  anything to do with memory volatility as suggested by an earlier
  article )
-- 
		    Brian Thomson,	    CSRI Univ. of Toronto
		    {linus,ihnp4,uw-beaver,floyd,utzoo}!utcsrgv!uthub!thomson