Hardware freaks Unite (on this one)

Tom Tkacik CS/50 tkacik at hobbes.cs.gmr.com
Thu Apr 25 07:52:30 AEST 1991

In article <102 at fbits.ttank.com>, Mariusz at fbits.ttank.com (Mariusz
Stanczak) writes:
|> In article <326 at kyzyl.mi.org>, tkacik at kyzyl.mi.org (Tom Tkacik) writes:
|> > On the 3b1 all of the memory runs at full speed.  The 68010 does not use
|> > any wait states, (even for expansion memory).  A cache
|> > cannot speed  it up at all.  Just think of your 3b1 as already having
|> > 4Meg of cache.
|> Thinking, thinking... hmmm.  Makes sense, and if that's the case, it just
|> shows how little I know about the hardware... the article in Electronic
|> Design indeed uses a '030 @ 33MHz, though there's nothing about wait 
|> states (only about a "retry mode" of the '030).  Is 'wait states' all
|> there is about lower then possible processor performance, or at the
|> 11MHz with 150ns memory such factors (if any) don't come into play?
|> (just curious).

The 3B1 uses a 68010 processor running at 10MHz.  The rest of the system
was designed to complement that processor.  The memory can be accessed by
the processor as fast as the processor can go (ie., no wait states).
Memory speed is not the bottleneck.  The processor is the bottleneck.

Maybe a little explaination of wait states is in order.
The 68010 uses 4 clock cycles to access one word of memory.
At 10MHz, that's 400ns.  The memory used in the 3B1 is 150ns.  With all of
the delays on the motherboard, (and through the 68010 itself), that work's
out about right.  When slower memory is used, (like the ROM for example),
400ns is not enough time to get the data from the memory to the processor.
When this happens, the processor must be stopped until the memory is ready.
The processor stops by being told to wait an extra clock cycle,
(adding 100ns to the available memory access time).  Because the processor
cannot do anything useful during this time, it is called a 'wait state'.

The 3B1 has a slow access mode (used for ROM and slow I/O devices)
that adds 5 wait states (extra clock cycles).
(900ns should be enough time for just about anything).
But all of the main memory uses no wait states.

Some of the newer workstations which use much faster processor speeds,
(up to 66Mhz in the case of the new HP 700 series), allows memory only about
15ns to give up its data.  Megabytes of memory that fast would cost a fortune.
Many waits states are required.  A good cache will allow the processor to
average fewer wait states. 

Higher performance in the 3b1 will only be gained by either
increasing the processor speed,
or by putting in a more powerful processor (68020 or 68030).

The problem with putting in a 68020 or 68030 has been hashed out before,
(the interrupt stack frame problem, which required kernel hacks to get it
to work).

The problem with putting in a faster 68010 is twofold.  First, I am not aware
of a faster 68010.  I think that 10MHz is the fasted Motorola made,
(though I am sure I will be corrected on that if I'm wrong:-).
If a faster 68010 could be found, then the clock speed could be increased.
Now, faster memory would be needed, (and a cache could be used).
However, I believe that the rest of the system was also designed to run
at 10MHz,
and more than just memory would start to fail.

Tom Tkacik
GM Research Labs
tkacik at hobbes.cs.gmr.com

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