Power Series Arch Description Request
George Drettakis
dret at DGP.TORONTO.EDU
Thu Sep 7 08:25:14 AEST 1989
I am interested in getting my hands on a document that will describe
the Power Series parallel architecture.
I am particularily interested in getting information on how the cache is
organised both physically and from a software point of view, the cache
consistency alg., how the hardware locks are implemented
(the bus structure etc), how spin locks interact with the unix multi-programming
environment, how the scheduler handles the "light-weight" threads and how they
get assigned to processors and how the virtual address space is managed.
A solid, public domain document (paper/tech report/memo/whatever) would be
more than appreciated.
Thanks,
--
George Drettakis (416) 978 5473 Dynamic Graphics Project
UUCP: ..!uunet!dgp.toronto.edu!dret Computer Systems Research Institute
Bitnet: dret at dgp.utoronto University of Toronto
Internet: dret at dgp.toronto.edu Toronto Ontario M5S 1A4 CANADA
Ean: dret at dgp.toronto.cdn -- Live where it's never below 25 deg. C.
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