SPARC assembly language question

[Tim Olson]

In article <1513 at brazos.Rice.edu> macom1!rikki at haven.umd.edu (R. L. Welsh) writes:
| X-Sun-Spots-Digest: Volume 8, Issue 123, message 12 of 17
| 
| The Sun-4 Assembly Language Reference Manual (PN:800-1788-??) states (p. 12):
| 
| "All BiCC instructions may indicate that the annul bit is to be 
| set by appending ',a' to the opcode; e.g. 'bgeu,a' ... "
| 
| What does setting the annul bit do and where can I get a better 
| description of SPARC assembly language commands than this particular
| document? 

Most RISC processors, for performance reasons, have "delayed branches",
meaning that the instruction immediately after a branch is executed
regardless of whether the branch is taken or not.  This is done because
the "delay-slot" or "branch shadow" instruction is already being decoded
by the time the branch is executed; it might as well try to do useful work
if it can.

Because the delay-slot instruction is executed regardless of the branch
condition, the instruction must be either beneficial (does useful work) or
innocuous (does not destroy needed values) for both branch paths.  If an
instruction that matches this description cannot be found, then a NOP must
be placed in the branch delay-slot.

Sometimes an instruction can be found that is beneficial in one direction
only.  To make use of these, some RISC processors implement "annulled
branches" -- these branches execute the delay-slot instruction for one
branch path only; in the other case, the delay-slot instruction is
dynamically annulled (turned into a NOP).  For the SPARC, the delay-slot
instruction is annulled if the branch is not taken.

You might try to find a SPARC architecture manual to find out more about
these features; one is available from Fujitsu.

	-- Tim Olson
	Advanced Micro Devices
	(tim at amd.com)