Sparcstation 1 oddities + request for enlightenment (Summ

[Paul E. McKenney]

Many thanks to:
	Dave Probert <probert%orcas at hub.ucsb.edu>
	dgh at sun.com (David Hough)
	djones%awesome.Berkeley.EDU at ucbvax.berkeley.edu (David G. Jones)
	guy at auspex.com (Guy Harris)
for providing the much-needed enlightenment.  The rest of this note consists
of my original posting, annotated with their responses.

>I noticed the following peculiarities of the Sparcstation 1:

>1. Although the fint[sdx], fintrz[sdx], fclass[sdx], fexpo[sdx],
>fscale[sdx], frem[sdx], and fquot[sdx] instructions are documented in the
>manual, the assembler rejects them as invalid opcodes.  Do these
>instructions exist in the underlying hardware, and, if so, could someone
>forward me their hexadecimal codes?

These instructions do not exist in either the Version 7 SPARC
architecture, or in Version 8, which is being finalized.  Some felt that
these instructions had been removed from the architecture before it became
official, and that the documentation has not yet caught up.  [This would
be unfortunate, some of the instructions look quite useful for those times
when one must get one's hands dirty in floating point, C's floating point
support being what it isn't.]

>2. The assembler appears to insert an extraneous ``st %g4, [%sp + 0x4]''
>instruction in front of any instruction that produces an extended result
>(e.g., fdtox or faddx).  Although this instruction looks like it should
>clobber the stack, it seems to act as a no-op -- despite the fact that the
>similar instruction ``st %g4, [%l0 + 0x4]'' does store into memory as I
>would expect.  Further, when I hand-assembled a small program without
>these extraneous instructions, it behaved the same as the program produced
>by the assembler containing the instructions.  Could someone please tell
>me the purpose of these apparently superfluous instructions and whether it
>is really safe to omit them (ah, the joys of cpp!)?

The extended result instructions are emulated by the kernel, rather than
being implemented in hardware.  The extra instructions make the kernel
emulation work better.

>3. I saw references to the ``annul'' bit in the manual, but no hint as to
>what its function is.  Could someone tell me what it does, or where to
>read about it?

The Sparc architecture has delayed branch; the instruction following the
branch instruction is always executed so that the effect of the branch is
``delayed'' one instruction.  The annul bit modifies this behavior so that
the instruction following the branch possessing the set annul bit will
only be executed if the branch -is- taken.

Once again, thanks to Dave, David, David, and Guy for the info!

				Thanx, Paul