Rumour about IBM benchmarks

[Michael Herman]

Two of the major reasons why floating-point performance is very strong
on the RS/6000 are (1) a floating-point multiple-add instruction that
executes in 1 instruction cycle (potentially in "parallel" with an
integer subscripting calculation instruction and a test-and-branch
instruction) and (2) a very powerful optimizer that was co-developed
with the processor hardware.

To many people, a "RISC instruction" was synonymous with a "simple
instruction" that executes in 1 cycle (or less).  IBM took the tact
that a RISC instruction could be complex as was possible as long as it
executed in 1 instruction cycle or less - that gave them a lot of
latitude in the instructions they implemented in silicon.

Although I am less familiar with them, there are supposedly a number of
C library (i.e. zero terminated) string functions what have also been
implemented directly in the silicon.