Help needed with DEC DEQNA on PDP 11/23+ Qbus

[Karl Kleinpaste]

Help!  I am trying (ever so desperately) to write a driver for a DEC DEQNA
Ethernet board to run on a PDP 11/23 Plus Qbus creature.  Unfortunately, the
documentation I have on it is a bit ambiguous and possibly contradictory.  I
have as yet not been able to get answers to a couple of questions on this
object.  Could somebody help me with the following:

(a) If you've got a driver for this thing (under any version of Unix, but Sys3
    is the way it will end up), could you mail it to me?  That would solve my
    problems entirely, and I could learn what is going on by studying your code.

(b) If you don't have a driver, but are familiar with the board, try to answer
    these questions for me:

	If I hand a 3-element Buffer Descriptor List to the DEQNA, and a short
	(i.e., 100-byte) msg comes in, I will of course get a Receive Interrupt.
	However, will the DEQNA also give up the remaining 2 unused buffers?
	That is, will Receive List Invalid also be true?  I sincerely hope so,
	because if it doesn't, then I have a sticky problem in partial-message-
	management, since the next message arriving could conceivably be >
	1024 bytes long, requiring > 2 buffers which are still committed to
	the DEQNA.  This presents all kinds of questions such as where the
	DEQNA will set "last buffer" (the LASTNOT bit active), and whether
	I will get another Rcv Int when that 2nd buffer is filled, even though
	additional data is waiting to be DMA'd in from the board's private
	buffer.

	What this really comes down to is, Does the DEQNA expect a single receive
	buffer to be large enough to hold a complete Ethernet message?  And does
	it expect a single BDL to constitute receive buffers for more than one
	message?

	Along these same lines, but from a different tack:  When transmitting, a
	Transmit Interrupt is generated when the message is finished leaving the
	board.  However, I do not know when Transmit List Invalid will be set.
	Will it be set as soon as the message to be transmitted has been moved
	to the DEQNA's internal buffer?  Or is Transmit List Invalid only set
	when the last transmit has completed (i.e., are Transmit List Invalid
	and Transmit Interrupt essentially the same thing)?

(c) Additionally, any textual sorts of descriptions of the various bit combina-
    tions of BDL elements would be welcome.  What I'm thinking of here are the
    uses of the VALID address descriptor bit, particularly on Receive completion,
    with respect to what constitutes the "end of the BDL" (table 4-2); is this
    the end as I supplied it to the DEQNA, or the "end" as it sees the end of
    a received message?  Similar thoughts/questions apply to the LASTNOT and
    ERROR/USED bits in the Status Word 1.

(d) How much of the Setup stuff is really needed?  As I look at it, it seems
    that I don't need much of it (possibly none); of course, I may want to
    override the supplied Ethernet address, so something along those lines
    will have to be done.  I'm not big on loopbacks at this point, either;
    other than hardware failures and hardware debugging, why do people use
    these modes?

If anyone can help me with these items, I would be *most* appreciative.  I
have been fighting these questions for 2 weeks, without getting anything of sig-
nificance accomplished.

I can be reached either at this address (cbosgd!osu-dbs!karl), but it is pre-
ferable to get to me at my office, address and phone below.

(Sigh...wimper...  Pain and agony!  Death and taxes!  [It's all the same, yano.])
-- 
"Real Men don't feed Usenet bugs!"
Karl Kleinpaste @ Bell Labs, Columbus	614/860-5107	{cbosgd,ihnp4}!cbrma!kk