A query about hardware emulator on a Unix system

[prindle at nadc.arpa]

Greetings,
I would like to enlist the aid of this net-newsgroup community in exploring
a potential hardware approach to upgrading a programming support enviroment.
We are also looking at strictly software approaches, but these currently
appear to have a high risk.

Requirements for the hardware approach:

a. A micro-programmable co-processor board which would interface directly with
   a high speed, state-of-the-art, computer which primarily runs a variant of
   Unix (preferrably System V, 4.x-BSD, or a happy marriage of the two).
   This board would be capable of emulating the instruction set architecture
   of a fairly primitive 30 bit militarized computer, specifically a Sperry
   (Univac) model CP-901/CP-642B.  I/O channel instructions within this ISA
   would be converted, by the board, into interrupt requests to be honored by
   the main processor and the Unix system.  The board would directly access
   a block of host computer virtual memory space (allocated by the Unix system)
   as the emulated computer's memory.  The emulator could be multiprogrammed
   under control of the main processor and the Unix system: i.e. it could be
   stopped or started at any time by the main processor, any and all of it's
   registers would be readable or writable by the main processor, and the DMA
   memory mapping may be altered by the main processor.

				      - or -

b. A high speed, state-of-the-art, dual or multi-processor computer, running
   Unix as above, in which one or more of the processors could be micro-
   programmed to emulate the CP-901/CP-642B ISA as above, and dedicated to
   that task, with the remaining processor(s) running the Unix system.

The goal is to run existing CP-901/CP-642B hosted support tools and some
application programs with a substantial throughput improvement over a system
which utilizes a physical CP-901/CP-642B computer.  The bottlenecks in such a
system are the physical computer resource itself (which, because it is loosly
coupled to the host computer, cannot be effectively multiprogrammed), and the
I/O channels which provide the only data paths in or out of the physical
computer.  A tightly coupled co-processor, sharing memory with the host
computer and with the ability for the host computer to intervene in it's
execution, eliminates these bottlenecks.  Since, additionally, state-of-the-art
hardware would be handling the CP-901/CP-642B emulation, as contrasted with the
antiquated (and militarized) hardware of the physical computer, it is reasonable
to expect at least a tenfold improvement in throughput (with a single
co-processor vs. using a single physical computer).

Possible candidates for the host computer are a Sun III, Dec 8600 or VAX 11/785,
AT&T 3B series, or anything else which might meet the above requirements.

I would appreciate any information which anyone might have about the existence
of such a system or a similar system which may have been implemented; as well as
any thoughts about the feasibility or potential efficiency of such a system.

Please netmail any reply directly to me, as I do not subscribe to all these
newsgroups.

Sincerely,
Frank Prindle
Naval Air Development Center
Warminster, Pa. 18974
Milnet: Prindle at NADC.arpa