Hardware freaks Unite (on this one)

[Mariusz Stanczak]

In article <1991Mar27.063904.10091 at chance.UUCP>, john at chance.UUCP (John R. MacMillan) writes:
> |...  Involved project no doubt, but if possible,
> |it'd be a safe way to boost performance of the system (as
> |opposed to trying to fit a more efficient processor and
> |making the OS angry ;-)).
> 
> Unless the cache is of physical memory and completely transparent the
> virtual memory system would have to know about it.  And if that is

	Yes it is.  In this particular implementation 8MB is directly
    mapped into 64KB of SRAM as 128 pages (page consists of 16KB 4-byte
    lines with the address space A2-15 covering the 16K lines for each
    page).


> the case, you probably wouldn't get as big performance wins because
> the physical memory is changing a lot to handle the virtual address
> space.

	That may be, though I wouldn't know.  The calculations are
    done for the 68030 with a statement "This design gives an average
    hit/miss ratio of about 85%" as the base for comming up through
    some more calculations that assume '030 clock cycle efficiency
    for reads and writes at 29% theoretical speedup.


> Of course the only way to find out is for one of you folks who know
> which end of a soldering iron to hold to try it out... :-)

	Yes... and in the mean time, would anybody with some formal
    training in this matters care to comment how a VM OS would affect
    the stated theoretical speedup factors that are based at physical
    mapping and R/W-instructions efficency of a given processor?

    -Mariusz
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