Protection in Cray

[David Heisterberg]

In article <1990Dec18.214228.25858 at agate.berkeley.edu> chiueh at sprite.Berkeley.EDU (Tzi-cker Chiueh) writes:
>                         I figure since Cray doesn't have virtual memory, maybe
>it can teach me something about achieving protection inexpensively. 
>Can anybody enlighten me about how Cray provides protection as normal virtual 
>memory systems offer, or where can I find useful description in this regard ? 

CRAYs (at least X and Y models) use base and limit register pairs (one
set for code, one for data) for each process.  The base register is added
to the logical address (as generated by the program) to give the physical
memory address.  It is, I think, the physical address that is checked
against the limit register, and, if out of bounds, a program or operand
range exception is generated.

With separate code/data base/limit registers code sharing is possible, but
I don't think it is much used.

That phrase, "normal virtual memory" - I just don't know what to make of it!
--
David J. Heisterberg		djh at osc.edu		And you all know
The Ohio Supercomputer Center	djh at ohstpy.bitnet	security Is mortals'
Columbus, Ohio  43212		ohstpy::djh		chiefest enemy.