Split I/D vs. Z8000

[George Robbins]

In article <1270 at ncoast.UUCP> allbery at ncoast.UUCP (Brandon Allbery) writes:
>Just one comment.  The Z8000 (to be precise, the Z8001) is segmented rather
>similarly to the 8086; but the Z8001 can handle memory management.  As a
>result, the PDP-11 style of memory management is used on Z8001's.

Well, it's really only like the 8086 in the sense that there's a large
model/small (segmented/non-segmented) distinction.  The segment registers
are handled quite diferently and there 64/128 of them when using a MMU(s).

The hardware programming model is very similar to a PDP-11 with separate
I&D space, although the Zilog unix port messes this up a bit.

>(Why Z8001?  The Z8000 doesn't have segment registers and can only address
>64K.  Period.)

No, the Z8000 is a generic title.  The basic Z8000 chip is packaged in either
at 40 (Z8002) or 48 (Z8001) pin package.  The 40 pin package does not bring
out the lines for the "segment" part of the address.  You still can have
I&D space for 128K total.  There are some other tricks you play, but they're
not useful outside of dedicated applications.
-- 
George Robbins - now working with,	uucp: {ihnp4|seismo|caip}!cbmvax!grr
but no way officially representing	arpa: cbmvax!grr at seismo.css.GOV
Commodore, Engineering Department	fone: 215-431-9255 (only by moonlite)