ELXSI System 6400 .... Information needed

[mat at amdahl.UUCP]

In article <120 at portal.UUcp>, jel at portal.UUcp (John Little) writes:
> In article <1946 at calmasd.CALMA.UUCP>, rfc at calmasd.CALMA.UUCP (Robert Clayton) writes:
> > a 10 processor test at Sandia Labs they got 10.1X the power of a single
> > processor.  
> 
> This is an interesting trick. Does anyone have a clue about how they
> got a greater than linear speedup?  Was this a cpu benchmark or did
> it include i/o?  

It was a fixed workload benchmark, running a variety of jobs as I recall.
It included I/O, but didn't measure anything but relative CPU throughput
capacity.

The greater than linear speedup occurs as a result of improved locality
of reference, reduced process switching, and better cache performance.
The ELXSI machine uses a message based architecture, and has cached
process context (registers, etc.) for 16 processes per processor. It
is very cheap to switch to a process that has a process slot, and very
expensive to switch to one that doesn't (process 0, the scheduler, must
be woken up to purge one process from its slot and set up the slot for 
the new one before the new one can run. A microcode dispatcher handles
the dispatching of "hot" processes that have a slot. Anyway, the existence
of more process slots reduces the number of very costly swaps, and, as a
byproduct, reduces cache miss rate, etc. Net result is that these savings
more than offset any interprocessor interference losses. Since there is no
memory sharing, this interference is small.

It should be pointed out that the message based architecture induces a very
high process switch rate, which makes these effects quite different than
would be observed in more traditional systems.

In a sense, the superlinear speedup is observed because of reducing overheads
which make the uniprocessor system run "slower than it should."

-- 
Mike Taylor                        ...!{ihnp4,hplabs,amd,sun}!amdahl!mat

[ This may not reflect my opinion, let alone anyone else's.  ]