SPARC architecture note: trap instruction implementation

[Mark Linimon]

The following information has been passed on to me, I thought I would pass
it along to the net.  Those not interested in implementation details of
the SPARC architecture should hit 'n' now to prevent boredom.

Mark Linimon
Mizar, Inc.
uucp: {sun!texsun, killer}!mizarvme!linimon

	The valid operand range of SPARC's Trap on Integer Condition Code
	(Ticc) instruction is 0...127 inclusive (a.k.a. "software trap
	numbers").  Hardware "happens" to map those values into "hardware
	trap types" 128...255.  This mapping is transparent to software
	(with minor exceptions).  Software should *not* be using the
	"hardware" trap types 128...255 as Ticc operands, blindly
	assuming that bits above the seventh one (bit 6) will be ignored.

	Granted, the "Rev 7" SPARC architecture document (800-1399-07)
	is vague about what happens when a Ticc operand is outside its
	specified 7-bit range.  It does not explicitly state whether the
	bits above bit 6 are "ignored", "unused", or "reserved".  More
	specific language may will likely appear in an upcoming revision of
	the manual.

	As with almost any processor architecture, the safe rule of thumb is:
	if the architecture doesn't specify how certain instruction bits are
	used, make 'em zero.  As for unspecified, "unused", or "reserved"
	bits in special registers, "when in doubt, ignore 'em when read, and
	zero 'em when writing them".  Consider anything else an explicit
	invitation for a demonstration of Murphy's Law.

---
mcl